A common requirement for an advanced electronic circuit and particularly for circuits manufactured as integrated circuits (“ICs”) in semiconductor processes are the use of memory for storage, and more recently, for discrete memory such as dynamic random access memory (“DRAM”), static random access memory (“SRAM”) and non-volatile devices such as flash memory. In some highly integrated devices, embedded memory arrays are provided as part of an integrated circuit that may include additional functionality. So called systems on a chip “SoC” devices may provide a processor, program memory, data storage memory, and other functions needed to implement an entire solution. Single chip cellphones, PDAs, etc., are possible using SoC technology. These advanced integrated circuits require embedded memory formed as part of an integrated circuit that also includes other functions, such as radio transceivers, microprocessors, microcontrollers, processors, cell phone circuitry and the like. Recently, the embedded memory designs are provided as “cores” or “macros” that are included with other functionality on an integrated circuit such as an application specific integrated circuit (“ASIC”).
Memory arrays may be formed with an array of memory cells arranged to place stored charge representing data onto one of or a pair of bit lines, or column lines, in response to a signal on an active row line, or word line. The timing of the memory cell access is therefore determined to a great extent by the duration of an active pulse on a word line.
The timing requirements of the memory array also affect the timing of the clock pulse and interface circuitry. In generating the word line signals to the memory array, address decoding circuitry is used. This address decoding circuitry receives a portion of a memory address into row decoders. The selected word line is determined from the row decoding logic circuitry after the address is presented. The address into the row decoders must be maintained for a period prior to the rising word line clock edge that will enable the word line drivers (set up time). In addition, the decoder outputs must be maintained at a steady value during the memory access, and remain steady for a period of time after the word line clock edge falls (hold time). These timing requirements place significant design constraints on the design of the overall integrated circuit.
The need for meeting these set up and hold time requirements typically results in the use of many latches in the interface circuits between the memory array and the remaining logic in the integrated circuit. These interface latches each require clocking and power and take up valuable silicon area. The timing requirements for the word line drivers thus create timing constraints which limit the design of the integrated circuit and place difficult constraints on the designer of new devices that include embedded memory arrays.
A continuing need thus exists for memory word line driver circuits and methods that overcome the disadvantages of the prior art approaches.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.